For many years, gate arrays have been used to provide quick-turnaround (quick-turn), low non-recurring-expense (NRE) semiconductor devices for a variety of purposes. Traditionally, wafers are processed up to but not including the first (bottom) metal layer, and saved in inventory. When a customer orders a device to be fabricated for a specific application (an application specific integrated circuit or “ASIC”), the customer only pays for the masks to configure the metal layers, and not the transistor layers below. Thus, NRE is reduced. The wafers can be completed quickly, since only the metal layers remain to be fabricated, reducing turn-around time.
Recently more and more layers of metal have been incorporated into gate array semiconductor devices. Rather than two or three layers of metal, six to eight layers of metal is now common. As a result, gate arrays are often no longer very low-NRE, or quick-turn. In order to regain the advantages of earlier gate arrays, several vendors have developed logic arrays, consisting of multiple, substantially identical logic cells, which can be configured for an application with either fewer or cheaper masks. In the case of fewer masks, the total number of metal layers and hence masks used to create the finished device often does not change. Rather, only a reduced subset of the total number of metal layers in a finished device is used to impart the custom configuration to the device. For example, so-called “one-mask” devices, in which only a single metal layer and hence a single mask imparts customization, can in theory reduce both NRE and turn-time.
In parallel with the above developments, many modem wafer fabrication facilities (“fabs”) that are capable of 0.18μ or better transistor channel lengths, have given up flexibility in manufacturing. Operators of these fabs are generally unwilling or unable to hold wafer inventory as had previously been done for gate arrays. This lack of inventory eliminates the quick-turn-time advantages of gate arrays. Also, these fabs typically require minimum orders of 25 to 100 wafers or more per mask set per month. Thus, the savings in NRE that a one-mask architecture can provide is typically less than the cost of a minimum order of wafers, reducing the advantages achievable from one-mask devices while leaving penalties of increased die area, increased power, and lower speed in place.
There have been attempts to achieve the benefits of advanced silicon from advanced fabs while providing the manufacturing flexibility needed to take advantage of quick-turn low NRE architectures. Laser-programming for prototyping ASIC's has been used, thus reducing turn-times. Another technique is reduced mask or one-mask finishing of advanced wafers. For these products, an initial architecture on an advanced wafer process is used, and then is held by the fab customer. The cell design of this initial architecture is often referred to as the “macro-cell.” A less advanced fab is then used to finish the wafers by configuring the few or single configuration masks. Such a process, split between two types of fabs, is often referred to as a “hybrid process.” A hybrid process has the advantage of low turn-times, low NRE, and high manufacturing flexibility in being able to handle small orders. However, the combination of reduced or one-mask programming and a less advanced process geometry to accommodate the finishing can result in low achievable logic density.